MAX1361MEUB+T【PDF 10/24 页】IC SYSTEM MON 10BIT 4CH 10-UMAX

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MAX1361/MAX1362

contains D7–D0. To read the next conversion result,

issue an ACK. To stop reading, issue a NACK.

When the MAX1361/MAX1362 receive a NACK, they

release SDA allowing the master to generate a STOP or

a repeated START condition.

Monitor Mode

Monitor-Mode Overview

The MAX1361/MAX1362 automatically monitor up to four

input channels. For systems with limited I2C bandwidth,

monitor mode allows the C to set a window by

programming lower and upper thresholds during initial-

ization, and only intervening if the MAX1361/MAX1362

detect an alarm condition. This allows an interrupt-driven

approach as an alternative to continuously polling the

ADC with the C. Monitor mode reduces processor over-

head and conserves I2C bandwidth.

The following shows an example of events in monitor

mode:

1) Fault condition(s) detected, INT asserted.

2) Host C services interrupt and send SMBus alert to

identify the alarming device. The MAX1361/

MAX1362 respond with the I2C slave address,

pending arbitration rules. (See the

SMBus Alert sec-

tion.)

3) The MAX1361/MAX1362 release the INT.

4) Host-C reads the alarm-status register, latched-

fault register, and current-conversion results to

determine the alarming channel(s) and course of

action.

5) Host C services alarm(s); adjusts system parame-

ters as needed and/or adjust lower and upper

thresholds.

6) Clears the alarm register. See the

Configuring

Monitor Mode section.

7) Monitor mode resumes.

8) If there is still an active fault, the device asserts INT

again. See step 1.

Writing SCAN1 and SCAN0 bits = [1,0] in the configura-

tion byte activates monitor mode. The MAX1361/

MAX1362 scan from channels 0 up to the channel

selected by [CS1:CS0] at a rate determined by the

scan delay bits. The MAX1361/MAX1362 compare the

conversion results with the lower and upper thresholds

for each channel. When any conversion exceeds the

threshold, the MAX1361/MAX1362 assert an interrupt

by pulling INT low (if enabled). The MAX1361/

MAX1362 set the corresponding flag bit in the alarm-

status register and write conversion results to the

latched-fault register to record the event causing the

alarm condition.

INT active state is randomly delayed with respect to the

conversion. Depending on the number of channels

scanned and the position in the channel scan

sequence, the maximum possible delay for asserting

INT is five conversion periods (34s typ, delay = 0,0,0).

Configuring Monitor Mode

To write monitoring setup data, set the monitor-setup bit

(bit 0 in setup byte) to 1 to extend writing up to 104 bits

(13 bytes) of monitoring setup data. The number of bits

written to the MAX1361/MAX1362 depends on whether

the part is in single-ended or differential mode and

whether the upper channel limit is set by [CS1:CS0]

(Table 9).

Terminate writing at any time by using a STOP or

repeated START condition. Previous monitoring setup

data not overwritten remains valid.

4-Channel, 10-Bit, System Monitor with Programmable

Trip Window and SMBus Alert Response

______________________________________________________________________________________

ACK

1, CH ADD, 10b/12b, 1,1

RESULT (2 MSBs)

RESULT N (8 LSBs)

tACQ

CONVERSION 1

tACQ

CONVERSION N

START

ADDRESS

FROM THE MASTER

1, CH ADD, 10b/12b

1,1 RESULT (2 MSBs)

RESULT (8 LSBs)

ACK

R/W

Figure 13. Example of Scan-Mode Conversions Using the External Clock, SCAN = 0,0 and 0,1

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